Memory devices may include memory cells for storing data. A memory cell may include a storage element coupled to a selector device. The storage element and selector device may be located at an intersection of two memory access lines (e.g., a word line and a bit line) in a memory array having a cross-point architecture. The selector may be coupled to a word line and the storage element may be coupled to a bit line in some architectures. The selector device may reduce leakage currents and allow selection of a single storage element for reading and/or writing.
Cross-point memory architecture may have, as selector device, an amorphous chalcogenide element characterized by a threshold voltage (VT). The storage element may also be a chalcogenide device in either a crystalline or amorphous state. The crystalline and amorphous states may correspond to different logic states (e.g., ‘1’ or ‘0’). In the amorphous state, the storage element may have the same threshold voltage (VT) as the selector device in some architectures. In other architectures, in the crystalline state, the storage element may have the same threshold voltage (VT) as the selector device. The overall cross-point memory cell is the series of the selector device and storage element. The memory cell may have either a low VT (VT_SET) when the storage element is in a crystalline state or a high VT (VT_RESET) when the storage element is in an amorphous state. The high and low threshold voltages which may be associated with the amorphous and crystalline states, respectively, may be representative of different logic states stored in the memory cell.
A memory array may have a memory voltage window budget that defines the maximum and minimum voltages for selecting memory cells within the memory array. Memory voltage window budget parameters may include the maximum VT_RESET voltage (VT_RESET_max) and the minimum VT_SET voltage (VT_SET_min) of the complete memory array of memory cells. At a first order, VT_RESET_max −VT_SET_min should be smaller than half of the maximum operating voltage available in order to properly access individual memory cells. VT_RESET_max and VT_SET_min may depend on one or more physical parameters of the selector device and/or the storage element (e.g., the chalcogenide chemical composition, thickness, cell-to-cell variability, etc.).
The cell-to-cell VT variability may increase the difference (delta) between VT_RESET_max and VT_SET_min such that the difference between VT_RESET_max and VT_SET_min is greater than the available voltage window. This may prevent the memory array from meeting the voltage window requirement. Currently, techniques to reduce cell-to-cell variability rely on the reduction of the variability of the physical parameters of the selector device and storage element that affect threshold voltage.